? semiconductor components industries, llc, 2013 april, 2013 ? rev. 5 1 publication order number: nvmfd5852nl/d nvmfd5852nl, nvmfd5852nlwf power mosfet 40 v, 6.9 m , 44 a, dual n ? channel logic level, dual so ? 8fl features ? small footprint (5x6 mm) for compact designs ? low r ds(on) to minimize conduction losses ? low capacitance to minimize driver losses ? nvmfd5852nlwf ? wettable flanks product ? aec ? q101 qualified and ppap capable ? this is a pb ? free device maximum ratings (t j = 25 c unless otherwise noted) parameter symbol value unit drain ? to ? source voltage v dss 40 v gate ? to ? source voltage v gs 20 v continuous drain cur- rent r j ? mb (notes 1, 2, 3, 4) steady state t mb = 25 c i d 44 a t mb = 100 c 31 power dissipation r j ? mb (notes 1, 2, 3) t mb = 25 c p d 27 w t mb = 100 c 13 continuous drain cur- rent r ja (notes 1, 3 & 4) steady state t a = 25 c i d 15 a t a = 100 c 10.6 power dissipation r ja (notes 1 & 3) t a = 25 c p d 3.2 w t a = 100 c 1.6 pulsed drain current t a = 25 c, t p = 10 s i dm 329 a operating junction and storage temperature t j , t stg ? 55 to 175 c source current (body diode) i s 40 a single pulse drain ? to ? source avalanche energy (t j = 25 c, v gs = 10 v, i l(pk) = 40 a, l = 0.1 mh, r g = 25 ) e as 80 mj lead temperature for soldering purposes (1/8 from case for 10 s) t l 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. thermal resistance maximum ratings (note 1) parameter symbol value unit junction ? to ? mounting board (top) ? steady state (notes 2, 3) r j ? mb 5.6 c/w junction ? to ? ambient ? steady state (note 3) r ja 47 1. the entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted. 2. psi ( ) is used as required per jesd51 ? 12 for packages in which substantially less than 100% of the heat flows to single case surface. 3. surface ? mounted on fr4 board using a 650 mm 2 , 2 oz. cu pad. 4. maximum current for pulses as long as 1 second are higher but are dependent on pulse duration and duty cycle. ordering information http://onsemi.com device package shipping ? v (br)dss r ds(on) max i d max 40 v 6.9 m @ 10 v 44 a ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. dfn8 5x6 (so8fl) case 506bt marking diagram 12.0 m @ 4.5 v NVMFD5852NLT1G dfn8 (pb ? free) 1500 / tape & reel 5852nl = specific device code for nvmfd5852nl 5852lw = specific device code for nvmfd5852nlwf a = assembly location y = year w = work week zz = lot traceability d1 d1 d2 d2 s1 g1 s2 g2 dual n ? channel d1 s1 g1 5852xx aywzz 1 d2 d1 d2 s2 g2 d2 d1 nvmfd5852nlwft1g dfn8 (pb ? free) 1500 / tape & reel
nvmfd5852nl, nvmfd5852nlwf http://onsemi.com 2 electrical characteristics (t j = 25 c unless otherwise specified) parameter symbol test condition min typ max unit off characteristics drain ? to ? source breakdown voltage v (br)dss v gs = 0 v, i d = 250 a 40 v drain ? to ? source breakdown voltage temperature coefficient v (br)dss /t j 37.3 mv/ c zero gate voltage drain current i dss v gs = 0 v, v ds = 40 v t j = 25 c 1.0 a t j = 125 c 100 gate ? to ? source leakage current i gss v ds = 0 v, v gs = 20 v 100 na on characteristics (note 5) gate threshold voltage v gs(th) v gs = v ds , i d = 250 a 1.4 2.4 v negative threshold temperature coefficient v gs(th) /t j 6.3 mv/ c drain ? to ? source on resistance r ds(on) v gs = 10 v, i d = 20 a 5.3 6.9 m v gs = 4.5 v, i d = 20 a 8.7 12 forward transconductance g fs v ds = 5 v, i d = 5 a 24 s charges and capacitances input capacitance c iss v gs = 0 v, f = 1.0 mhz, v ds = 25 v 1800 pf output capacitance c oss 240 reverse transfer capacitance c rss 180 total gate charge q g(tot) v gs = 4.5 v, v ds = 32 v, i d = 20 a 20 nc threshold gate charge q g(th) 1.5 gate ? to ? source charge q gs 5.5 gate ? to ? drain charge q gd 10.9 total gate charge q g(tot) v gs = 10 v, v ds = 32v, i d = 20 a 36 nc switching characteristics (note 6) turn ? on delay time t d(on) v gs = 4.5 v, v ds = 32 v, i d = 20 a, r g = 2.5 12 ns rise time t r 52 turn ? off delay time t d(off) 21 fall time t f 13 turn ? on delay time t d(on) v gs = 10 v, v ds = 32 v, i d = 20 a, r g = 2.5 12 ns rise time t r 8.0 turn ? off delay time t d(off) 27 fall time t f 5.0 drain ? source diode characteristics forward diode voltage v sd v gs = 0 v, i s = 20 a t j = 25 c 0.84 1.1 v t j = 125 c 0.69 reverse recovery time t rr v gs = 0 v, d is /d t = 100 a/ s, i s = 20 a 22.3 ns charge time t a 12.8 discharge time t b 9.4 reverse recovery charge q rr 15.2 nc 5. pulse test: pulse width = 300 s, duty cycle 2%. 6. switching characteristics are independent of operating junction temperatures.
nvmfd5852nl, nvmfd5852nlwf http://onsemi.com 3 typical characteristics 7.0 v figure 1. on ? region characteristics figure 2. transfer characteristics v ds , drain ? to ? source voltage (v) v gs , gate ? to ? source voltage (v) 5 2 1 0 0 100 4.0 3.5 3.0 2.0 4.5 5.0 figure 3. on ? resistance vs. v gs figure 4. on ? resistance vs. drain current and gate voltage v gs , gate ? to ? source voltage (v) i d , drain current (a) 9 8 710 6 5 4 2 0.006 150 50 25 0.0125 0.0150 0.0200 0 figure 5. on ? resistance variation with temperature figure 6. drain ? to ? source leakage current vs. voltage t j , junction temperature ( c) v ds , drain ? to ? source voltage (v) 175 125 100 75 25 0 ? 25 ? 50 0.8 1.0 40 25 20 15 10 5 10,000 100,000 i d , drain current (a) i d , drain current (a) r ds(on) , drain ? to ? source resistance ( ) r ds(on) , drain ? to ? source resistance ( ) r ds(on) , drain ? to ? source resistance (normalized) i dss , leakage (na) 5.0 v 3.4 v 3.0 v 10 v v ds 10 v t j = 25 c t j = 125 c t j = ? 55 c 0.004 i d = 20 a t j = 25 c v gs = 4.5 v t j = 25 c v gs = 10 v 50 i d = 20 a v gs = 10 v v gs = 0 v t j = 150 c 2.5 0.002 0.008 1.2 1.4 0.010 125 0 4.4 v 3 0 75 150 25 0.020 0.0050 1.6 2.2 50 0.0075 0.0175 4 25 75 150 50 100 125 3 75 125 100 1.8 0.6 1,000 100 t j = 25 c 3.6 v 4.0 v 0.012 0.014 0.016 0.018 0.0100 0.0025 2.0 150 30 35 t j = 125 c
nvmfd5852nl, nvmfd5852nlwf http://onsemi.com 4 typical characteristics q gs figure 7. capacitance variation figure 8. gate ? to ? source and drain ? to ? source voltage vs. total charge v ds , drain ? to ? source voltage (v) q g , total gate charge (nc) 40 20 30 10 0 0 500 figure 9. resistive switching time variation vs. gate resistance figure 10. diode forward voltage vs. current r g , gate resistance ( ) v sd , source ? to ? drain voltage (v) 100 10 1 10 100 0.90 0.85 0.80 0.75 0.65 0.60 0 25 50 figure 11. maximum rated forward biased safe operating area v ds , drain ? to ? source voltage (v) 100 10 1 0.1 0.1 1 10 c, capacitance (pf) v gs , gate ? to ? source voltage (v) t, time (ns) i s , source current (a) i d , drain current (a) v gs = 0 v t j = 25 c c iss c oss c rss q t v ds = 32 v i d = 20 a v gs = 4.5 v t d(on) t r t f t j = 25 c v gs = 0 v v gs = 10 v single pulse t c = 25 c r ds(on) limit thermal limit package limit 100 s 10 ms 1 ms dc 1500 1000 1.05 0 2 01015203035 t j = 25 c v ds = 32 v i d = 20 a 100 10 s 25 5 2000 2500 6 8 10 4 q gd t d(off) 40 1000 0.70 75 100 0.95 1.00
nvmfd5852nl, nvmfd5852nlwf http://onsemi.com 5 typical characteristics figure 12. thermal response pulse time (sec) 0.01 0.001 0.0001 0.00001 0.000001 0.01 0.1 1 10 100 r ja ( c/w) 0.1 1 10 100 1000 10% duty cycle = 50% 20% 5% 2% 1% single pulse
nvmfd5852nl, nvmfd5852nlwf http://onsemi.com 6 package dimensions dfn8 5x6, 1.27p dual flag (so8fl ? dual) case 506bt issue e *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 1.27 0.75 1.40 3.70 4.56 8x pitch 6.59 4.84 1.00 dimension: millimeters 2.30 4x 0.70 5.55 4x 0.56 2x 2.08 2x m 3.25 h ??? 3.50 ??? notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from the terminal tip. 4. profile tolerance applies to the exposed pad as well as the terminals. 5. dimensions d1 and e1 do not include mold flash, protrusions, or gate burrs. 6. seating plane is defined by the terminals. a1 is defined as the distance from the seating plane to the lowest point on the package body. 7. a visual indicator for pin 1 must be located in this area. 1234 5 6 top view side view bottom view d1 e1 h d e b a 0.20 c 0.20 c 2x 2x dim min millimeters a 0.90 a1 ??? b 0.33 c 0.20 d 5.15 bsc d1 4.70 d2 3.90 e 6.15 bsc e1 5.70 e2 3.90 e 1.27 bsc g 0.45 k 0.51 l 0.48 a 0.10 c 0.10 c 14 8 e 8x d2 b1 e2 b a 0.10 b c 0.05 c l detail a a1 c 4x 5 max ??? ??? 0.42 ??? 4.90 4.10 5.90 4.15 0.55 ??? 0.61 m n 1.80 2.00 7 8 n pin one identifier note 7 note 4 c seating plane detail a note 6 4x k note 3 d3 1.50 1.70 b1 0.33 0.42 4x d3 g 4x detail b detail b alternate construction k1 0.56 ??? k1 3.75 12 max 1.10 0.05 0.51 0.33 5.10 4.30 6.10 4.40 0.65 ??? 0.71 2.20 1.90 0.51 ??? on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 nvmfd5852nl/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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